Xilinx, a leading FPGA provider, offers a variety of soft and hard IP cores to its customers. These IP cores represent hundreds of communication standards, memory interfaces, DSP functions, floating point operators, interconnects, and CPUs. However, the company faced a significant challenge in testing its IP designs with all relevant combinations of parameter values. This exhaustive process required testing all major design modes with all possible data-width values. The conventional solution of creating an exhaustive permutation set of all parameters was not feasible due to the high number of combinations and the long turnaround time for running a regression. Xilinx needed a solution that could randomly generate parameter sets, considering the legal values of all parameters and the dependencies between them, while avoiding parameter set repetition and redundant duplication of test suite regressions.

Xilinx is the world’s leading provider of All Programmable FPGAs, SoCs, MPSoCs and 3D ICs, enabling the next generation of smarter, connected, and differentiated systems and networks. Driven by the industry-wide shifts towards Cloud Computing, SDN/NFV, Video Everywhere, Embedded Vision, Industrial IoT, and 5G Wireless, Xilinx innovations enable these applications that are both, software defined, yet hardware optimized. Xilinx’s portfolio of software defined and hardware optimized solutions include proven C and IP based design tools that support the development of ‘software defined hardware’, and a new family of software development environments that supports the development of ‘software defined systems’. With this unique combination, Xilinx is addressing the rapidly growing demands for programmability and intelligence with software, while enabling >10X the bandwidth, 1/10th the latency and power, and flexible any-to-any connectivity with optimized hardware.