Defying Convention to Achieve Faster Signal and Simulation Speeds

• 分析与建模 - 预测分析
• 应用基础设施与中间件 - 数据交换与集成
• 应用基础设施与中间件 - 数据可视化

• 电子产品
• 半导体

• 产品研发
• 质量保证

• 质量预测分析
• 制造过程模拟
• 数字孪生

• 软件设计与工程服务
• 系统集成

In the electronics and computer hardware industry, optimizing the design of high-speed interconnects in printed circuit boards (PCBs) is a significant challenge. As electronic devices become smaller, the size and spacing of package interconnects must be scaled down, making computational design optimization more time-consuming. Higher frequency interconnects consume more power, and the geometry and materials of these interconnects need to be redesigned to minimize power consumption and prevent signal loss. This is particularly crucial for PCBs, which are used in a wide range of electronic devices. Full-wave electromagnetic simulation is necessary to model signal propagation in these interconnects, but solving the complete set of Maxwell’s equations without simplifying assumptions is computationally intensive. This complexity is compounded by the need to account for non-negligible electromagnetic couplings and impedance mismatch in complex 3D structures, which can cause crosstalk and reflection, compromising signal integrity.

Intel, a leader in the electronics and computer hardware industry, is renowned for its powerful computing clusters and servers used to efficiently simulate and optimize designs. The Intel Guadalajara Design Center, in particular, has developed innovative optimization methods combining space mapping algorithms and electromagnetic simulation to improve signal speed and integrity in package interconnects. This approach is crucial for the development of high-speed interconnects in printed circuit boards (PCBs), which are integral to almost every electronic device, from handheld computers and cellphones to state-of-the-art satellite communication systems. The center's researchers and engineers leverage multiphysics simulation software and unconventional design optimization techniques to address the challenges of making electronic devices smaller and more efficient. Their work ensures that the latest high-speed interconnect technology is available in less time, maintaining Intel's position at the forefront of technological innovation.

To address the challenges of optimizing high-speed package interconnects, Intel engineers at the Guadalajara Design Center utilized COMSOL Multiphysics® software to develop a model of a single-ended interconnect line embedded in a PCB structure. This model allowed them to perform full-wave electromagnetic simulations, which are essential for accurately modeling signal propagation in interconnects operating at higher frequencies. The simulations accounted for non-negligible electromagnetic couplings and impedance mismatch in complex 3D structures, which are critical factors in maintaining signal integrity. To further enhance the optimization process, the engineers implemented a Broyden-based input space mapping optimization algorithm. This approach involved solving two separate interconnect models in COMSOL: a coarse 2D model and a fine 3D model. The coarse model provided a fast result by neglecting electromagnetic losses and using a very coarse mesh, while the fine model offered greater accuracy with a much finer mesh. The space mapping algorithm, implemented in MATLAB® software, aimed to find the 3D model design parameters that closely matched the optimal 2D model response. This method significantly reduced the overall computation time, allowing the interconnect design parameters to be optimized within just four iterations. The results showed a substantial reduction in reflected signal for the optimized design compared to the original fabricated interconnect prototype.

• The use of full-wave electromagnetic simulation in COMSOL Multiphysics® allowed Intel engineers to accurately model signal propagation in high-speed package interconnects, accounting for critical factors such as electromagnetic couplings and impedance mismatch.
• The implementation of a Broyden-based input space mapping optimization algorithm significantly reduced the overall computation time, enabling the optimization of interconnect design parameters within just four iterations.
• The space mapping approach involved solving both coarse 2D and fine 3D models, providing a balance between speed and accuracy in the optimization process.

• Simulations were run on a high-performance server with dual Intel® Xeon® X5670 CPU at 2.93 GHz and 160 GB of RAM.
• The space mapping algorithm allowed the interconnect design parameters to be optimized within just four iterations.